Main Components
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| FCS |
Fast Control System controlles the
first level acquisition |
| FE |
Front End of detector carrying ether an ASD8 or
a HELIX |
| FED |
Front End Driver connects FE to SLB
and FCS. There are 4 kinds of FEDs used in HERA-B: The
"analog FED" for the inner tracker and the silicon vertex detector,
the TYDC board for th eouter tracker, the HIT FED for th emuon
system, the RICH, the High-Pt system and the TRD, an ADC FED for the ECAL. |
| FLT |
First Level Trigger
(list of components) |
| FLT-Link |
Link from FED to FLT for FLT
data |
| SLB |
Second Level Buffer (made out of SHARC Cluster boards) |
| EVC |
Event Controller controlles the SLT and TLT farms and the buffers
in the SLB. See its structure scheme. |
| SLT |
Second Level Trigger (list
of components) |
| Switch |
Is a set of SHARC Cluster boards which route
data between the SLT nodes and the SLBs |
| TLT |
Third Level
Trigger |
| 4LT |
Fourth Level
trigger; sometimes named "the Farm" |
| Farm |
Processor
Farm - often used for the L4 Farm |
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FLT Components
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| Pretrigger |
Muon Pretrigger, Electron Pretrigger and High Pt Pretrigger are the
particle identification devices of the FLT |
| TFU |
Track Finding Unit is part of
FLT |
| WM |
The Wire Memory stores
the detector data on the TFU |
| TPU |
Track
Parameter Unit is part of FLT |
| TDU |
Trigger
Decision Unit is part of FLT |
| Test Board |
used for all FLT board testing;
used in the '97 run as trigger board |
| L1SIMU |
Fortran based FLT simulation |
| FLTsim |
new C++ based FLT Simulation |
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SLT and TLT Components
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| SLP |
Second Level Process. Is the hardware running the SLT
and TLT as well as the the software framework integrating
the SLT, TLT and EVA processes.
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| SLR |
Second Level Request Handler running on SLB. It
is now OBSOLETE! Its functionality is covered
by SDS. |
| SDS |
SLB data Server running on SLB; Serves requests
by SLT, TLT and monitors. It is replacing
the SLR. |
| SRQ |
Second Level requestor running on the SLT processing node |
| MAP |
Second Level Mapper mapping the Coordinates of an ROI to channel numbers |
| CLU |
Second Level Clustering (Cluster and Sparcify the channels in ROI) |
| PAM |
Second Level Reverse Mapper |
| L2SIMU |
Level 2 Simulation and Development Framework |
| EVA |
Event Assemply takes place at the SLP. |
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4LT Components
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| OARTE |
Online Verion of ARTE running on the L4 Farm |
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DAQ SHARC Software
Components
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| BPM |
Buffer Pool Management for the SHARC and UNIX. It manages buffers
und queues thereof |
| RPS |
Really Powerful SHARC messaging is part of the kernel library |
| Kernel |
SHARC Kernel library (it includes BPM,RPS,DCD) |
| DCD |
DMA Chain Driver for SHARC links |
| BMG |
Buffer Manager is a System placed in the EVC and
SLB and operates the buffers for the Second Level |
| MBM |
is the master buffer manager running on EVC |
| SBM |
is the slave buffer manager running on the SLB |
| FLTR |
First Level trigger Receiver |
| MON |
Monitor of EVC |
| SLTS |
Second level trigger sender |
| MLTR |
Mid Level Trigger receiver |
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DAQ Run & Slow Control
Components
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| RPM |
Real Powerful Messaging; HERA-B messaging system |
| RPI |
Real Programmers Interface is a layer below RPM in the unix
message passing system |
| RPB |
Really Pretty Basic layer of the UNIX RPM system |
| EMG |
Event Manager: handle events in shared memory partitions |
| TBD |
Table Based Data Base |
| HBDIS |
Display tool for TBD |
| HBEDIT |
Editor fot TBD |
| HTable |
Histogramm Tables; Histogramming
based on TBD |
| RHP |
Remote Histogram Package; Histogramming
on multiple distributed sources |
| SMC |
State Maschine Control: the HERA-B state machine package |
| EBM |
Event Buffer Manager |
| ESP |
Event Swap Package: swap bytes to allow cross platfrom data
exchange for raw data events |
| ETB |
Event Tool Box: utilizes access of event data |
| RNP |
Run Name Package: utilizes lookup
of run specific processes |
| DMON |
Data Monitor Framework: skeleton
for component specific monitoring processes |
| TG |
Trigger Generator: generate FCS trigger with handshake to
EMG partition | .
| RSM |
Resource Manager |
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Electronics Parts
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| PCI2SHL |
PCI to SHARC link Converter |
| CC |
Crate Controller for VME crates |
| PPC |
Power
PC is a Processor from Motorola; Verions are 601, 603e, 604e |
| PPRO |
Pentium Pro
Processor from Intel; running at up to 200MHz |
| ASD8 |
Amplifier Shaper Discriminator for Straw Tube sugnals designed by Mitch
Newcommer from University of Pennsilvenia. It is used as FE for the OT,
Muon System, RICH, High-Pt and TRD |
| ASDBLR |
Same as ASD8 but with different shaping time and two discriminators
with potentially different thresholds. |
| HELIX |
Preamplifier and analog pipeline for Silicon detector signals developped
at the ASIC Lab
in Heidelberg. It also contains discrimiators to allow the output of
trigger signals. |
| TDC |
Time To Digital converter used in the outer tracker as FED |
| SHARC |
Super Harvard
ARchitecture Computer is a ADSP form Analog Devices |
| SHARC Cluster |
6u VME board carrying 6 SHARC
chips |
| ASIC |
Application Specific Integrated Cirquit |
| ADSP |
Advanced Digital Signal Processor |
| DSP |
Digital Signal Processor |
| Autobahn |
Data Link Chip for 100 MByte/s produced by Motorola.
We are using th epresent (4/97) version. The next Version will have
a reveised parallel Interface which is incompatible with the present one.
Motorola (Neumann) claimes (on 28th April 1997), that the present
version will be supplied in parallel with the next one... . |
| LVDS |
Low Level Differential
Signaling; this
technoligy is used for signal transmission in the FCS and
on the new SHARC board for short distance Links.
TTL to LVDS transceivers are DS36C200,
receivers are DS90C032
and drivers are DS90C031
all from NS |
| EPLD |
Erasable Progammable Logic Device (in HERA-B used devices are MACHs
from AMD) |
| FPGA |
Field Programmable Gate Array (in HERA-B used devices are XILINX,
LATTICE, FLEX) |
| PAL |
Programmable Array Logic |
| XILINX |
is an FPGA of a specific Vendor; sometimes used as synonym for FPGA |
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Vendors
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| AMD |
Advanced Micro Devices is a vendor of chips |
| AD |
Analog Devices is a manufacturer
of Chips and produces the SHARC |
| CETIA |
Producer of VME electronics; we buy PPC boards there |
| Intel |
Company producing Processors |
| MSC |
Distributor/Developper of electronics;
builds the TDC boards, SHARC Clusters
and HIT FEDs |
| Motorola |
Company producing Processors
and Link Chips |
| NS |
National Semiconductor produces
LVDS devices and such |
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Other Terms
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| ROI |
Region Of Interest: Used to specify a window for a track search first
by the Pretrigger, then in the FLT
and also in the SLT |
| RCS |
Run Control System: Is a system build out of software components
to control the data taking. It includes the control of data streams and
system parameters. |
| SCS |
Slow Control System: The part of the RCS
which deals with the status of the detector which is not data path related.
It is an integral part of the RCS. |
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