HERA-B Data AcQuisition Notes DAQ
overview page
DAQ Notes (most recent first)
-
HERA-B DAQ Nameing Conventions
-
Mass Storage Management on the Farm
- Online Library Installation Guide
- Data Driven Second Level Buffer Manager
- Architecture talk at DAQ96 and paper
- DS link based SLT proposal
- All SHARC based SLT proposal
- New SHARC board address map
- SHARC board experience
- The Event Controller
- Data formats for the HERA-B DAQ
- HERA-B
Data Chain (A.Gellrich) (30-Oct-96)
- Mass
Storage and Computing Requirements for HERA-B (H.Albrecht, A.Gellrich,
T.Oest, I.Siccama)
- Naming
of Raw Data Tables in Arte (H.Albrecht, A.Gellrich)
- Conversion
and Storage of Event Data in the Test Run 1996 (H.Albrecht, A.Gellrich)
- Method's and Results of the TDC-Hit-Chip
Tests at Heidelberg
- Implementation of the SLB using SHARCs
- Specifications of the next generation SHARC
board
- On the Readout Buffer Deadtime
- General Computing Enviroment
and Network Configuration and Ethernet Cabling (Room 201)
- Muon T-Link for 1996
- SHARC board description (not ghostview-able
but printable)
- Online Software for 1996
- Computing Hardware 1996
- Implementation of the Fast Control System
- Ground Connection Design Rules
- System Software Breakdown (Dec 7 95 meeting)
- Specification of TRD Readout System (S.Bobkov,P.Neustroev,E.Spiridenkov,V.Stepanov)
- Clustered SLB approach
- Structure of HERA-B Control System
- analog FED design (M.Feuerstack)
- Comparison of analog FED design approaches
(M.Feuerstack)
- Common DAQ Architecture See also the new Switch
Architecture in 1997.
- First approach to a Fast Control System
- state of
Front/End Nov 1 94
- Proposal
for Trigger & DAQ, September 20 1994 (H.Leich, U.Gensch, P.Wegner)
last update 24/6/97 editors: Uschi Djuanda <djuanda@x4u2.desy.de>,
D.Ressing, John Zweizig <zweizig@x4u2.desy.de>