FLT-Notes
FLT efficiency maps
FLT online efficiency map
FLT online initialization software
Prospects of operating FLT without MU4
Channel masking in the FLT
Hera-B First Level Trigger Test Vector Test
Mapping of the OTR and the Muon detectors for the First Level Trigger
MU1 efficiency at FLT
Untersuchungen der Myon-Pretrigger-Elektronik fuer das HERA-B Experiment.
(HERA-B 97-145, in german)
User documentation for the FLT-testboard system software
(german)
Internal guide for the FLT-testboard system software
(german)
Status October 1996
(HERA-B 96-243)
L1SIMU detector geometry definition:
HTML
,
PS 133K
User guide for the ARTE version of L1SIMU:
HTML
,
PS 45K
Trigger Link Board requirements
Message and Process definition (DIN A4)
(booklet version)
(old version)
Wire Memory Definition and Implementations Overview
(HERA-B 96-245)
Discrete Wire Memory (default implementation)
Detector Placement for the '96 Run
(HERA-B 96-242)
Tracking calculus
Message board documentation (PS, 5M from Mannheim)
Kinematics calculus
The input connections for the FLT superlayer TC2
Data format for theMuon Pixel Mapping Boards
(30 Nov)
Preliminary Documentation of the PMG
Preliminary mapping of the muon detectors to the FLT
Preliminary scheme of the inter-TFU-mapping
The HERA-B FLT TFU Pipeline Flow Documentation (Postscript)
The HERA-B FLT TPU LUT Addressing Scheme
The HERA-B FLT TPU Pipeline Flow Documentation (Postscript)
TFU mapping of the OTR for the FLT system at HERA-B
How to reduce the electronics for MX1 chamber
Link Related Notes
Documentation of the Data Link Board which will be used for the MUON and the OTR systems:
OTR/MUON_FLT_LB documentation
Manual for programming the FLT linkboards
Summary of the Mapping Constraints of the FLT_LB:
FLT_LB constraints
Results of the mechanical cabling tests of the OTR FED crates:
OTR FED cabling
BACK
Concerned persons:
Holger Fleckenstein