Minutes DAQ/SLT/TLT/4LT meeting 6 May, 1997. Hamburg Agenda: 1. Organizational issues DR 2. Status of system definition DR 3. Discussion all 4. SLB data server MM 5. Event building concept for the 97 run SF 6. rpi/kernel JL 7. Link Synchronization GW 8. SLT farm hardware MD 9. Farm monitoring, slow control MD 10. Sharc board status DR 11. Status of the SHARC-to-PCI interface card AG 12. Installation scenario for the 97 AIX-farm RD 13. '97 SLT demonstration PK 14. Application software frames on L3 and L4 AG 15. Refit status MM for SE 16. Magnet traversal status SX 17. MC status & ideas for a L3 environment SS 18. Review and schedule update Present: M. Dam, R. Dippel, A. Gellrich, J.D. Hansen, W. Hofmann, P. Kreuzer J. Luedemann, M. Medinnis, C. Padilla, B. Rensch, D. Ressing ,S. Scharein S. Schmidt, A. Schwarz, F. Sun, G. Wagner, S. Xella, J. Zweizig Scribe: M. Medinnis It was agreed that the minutes should contain primarily a summary of decisions made and discussion over and above that contained in prepared talks. Copies of transparencies can be obtained through the usual channels. Organizational issues: The new "DAQ Projects" page under "DAQ" is intended to show responsibles for the various parts of the system. The person listed as responsible is asked to provide an html page with a brief summary of his or her view of the task to be accomplished. Status of system definition: General agreement as to how the system should be broken down had not been reached as of this meeting. The primary disagreement is in how finely to break the system down into modules with well-defined interfaces. At issue is to either have a coarsely-grained system with no interfaces defined below EVC and BMG or to further break these systems down into MBM:(SBM,MBM), EVC:(FLTR,SLTR,SLTS) and to define another system: SDS which is distinct from SBM. According to the latter philosophy, where components of different systems reside on different nodes, they should communicate via RPI messages unless this proves impossible because of latency or any other practical consideration. After much discussion, BR agreed to produce two definition documents one for MBM and the other for EVC. The documents will reflect finer-grained approach mentioned above. It is not yet clear who will implement the design. (BR has commitments at CERN starting in June.) It was pointed out (BR) that the data-base is still not well enough defined and that time is getting short. There was not disagreement on this point. SLB data server: The proposal to have some capability to insert data into the raw data buffers was accepted although this capability may only be used outside of normal data-taking periods. Event builder: SF pointed out the need to have some way to either know when a message has actually left a node, or to have a blocking send in RPI. Either will require an extension to RPI. It was agreed that this should be added. DR favors the latter approach. RPI/kernel: status: defined, implementation underway DCD, RPI: written, being debugged SIO, VME: written, being debugged RPB: written and debugged RRB: being written now Missing: run-time environment, interupt handling Full implementation now due for 1/6 (two week delay) SLT farm hardware: Need to decide whether or not to have a flash-disk. In addition, a floppy disk drive is favored: surest way to gain access to cpu in event of a failure. The new ASUS "smart motherboards" were looked into. They are not appropriate for SLT use since they are interupt driven and also not compatible with LINUX. The CAN bus card is being planned to have a PCI form factor. But since it doesn't use the bus, could it be given an ISA form factor? This would liberate a PCI bus slot which may be useful, particularly if the same card finds its way into the 4LT farm. MD will check. (He notes that 3.3 v is not available on ISA, so this could not be monitored.) NBI plans to bring 5+1 PentiumPro nodes to DESY and have them set up by Aug. 1. The 5 will be divided between SLT and TLT. The sixth is used for control. SHARC board status: - Delivery of 1st board delayed by one week to Friday in a week. - End June, expect 10 boards. - JL estimates 1 man-day to adapt existing software SHARC/PCI interface: "On schedule". It was pointed out that it would be useful to have tighter error bars than "summer monthes", now that the nominal delivery date (15 July) is fast approaching. MM will check that the meaning of "prototype delivery" is consistent between the two DESYs. 4LT hardware: Discussion: At 7kDM, the PowerPC 604e is more expensive per node than a Pentium/LINUX. It's not clear that the increased performance of the 604e compensates. A side-by-side cost comparison is needed. Also needed: benchmarks for reconstruction programs on LINUX. Uniformity (and probably also cost) argue in favor of the Pentium solution. This solution cannot be chosen unless the reconstruction program can be made to run on LINUX. Ideas for the L3 environment: SS presented a scheme for developing L3 code. The idea is to write L3 code in C++ using the C++ interface to Arte but to substitute simplified memory management for Zebra. It was pointed out (WH, DR) that it is important to be able to run "standard" reconstruction software such as Ranger at L3. (This is the original motivation for L3.) Therefore, the FORTRAN interface must also be provided. The proposal then is tantamount to a full-scale substitution of Zebra. DR further commented that priority now should be given to studies of where suppression can be obtained level 3. Such studies can most quickly be done in the current Arte framework. Schedule update: A revised schedule based on the outcome of this meeting will be prepared by DR and posted on the web page.